#define DMA_BASE_ADDR       0x40410000
#define MM2S_DMACR          0x00
#define MM2S_DMASR          0x04
#define MM2S_CURDESC        0x08
#define MM2S_CURDESC_MSB    0x0C
#define MM2S_TAILDESC       0x10
#define MM2S_TAILDESC_MSB   0x14
#define MM2S_SA             0x18
#define MM2S_SA_MSB         0x1C
#define MM2S_LENGTH         0x28
#define SG_CTL              0x2C
#define S2MM_DMACR          0x30
#define S2MM_DMASR          0x34
#define S2MM_CURDESC        0x38
#define S2MM_CURDESC_MSB    0x3C
#define S2MM_TAILDESC       0x40
#define S2MM_TAILDESC_MSB   0x44
#define S2MM_DA             0x48
#define S2MM_DA_MSB         0x4C
#define S2MM_LENGTH         0x58

typedef unsigned int u32;

typedef struct {
    u32 nextdesc;
    u32 nextdesc_msb;
    u32 buffer_addr;
    u32 buffer_addr_msb;
    u32 reserved1;
    u32 reserved2;
    u32 control;
    u32 status;
    u32 APP0;
    u32 APP1;
    u32 APP2;
    u32 APP3;
    u32 APP4;
} SG_Descriptor;

